/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
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* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/

/***********************************************************************************************************************
* File Name    : r_cg_tau.h
* Version      : Applilet4 for R7F0C903-908 V1.00.01.02 [30 Nov 2017]
* Device(s)    : R7F0C908B
* Tool-Chain   : CCRL
* Description  : This file implements device driver for TAU module.
* Creation Date: 2022/9/5
***********************************************************************************************************************/
#ifndef TAU_H
#define TAU_H

/***********************************************************************************************************************
Macro definitions (Register bit)
***********************************************************************************************************************/
/*
    Peripheral Enable Register 0 (PER0)
*/
/* Control of timer array unit 0 input clock (TAU0EN) */
#define _00_TAU0_CLOCK_STOP                     (0x00U) /* stops supply of input clock */
#define _01_TAU0_CLOCK_SUPPLY                   (0x01U) /* supplies input clock */

/*
    Timer Clock Select Register 0 (TPS0)
*/
/* Selection of operation clock (PRS003 - PRS000) */
#define _0000_TAU_CK00_fCLK_0                   (0x0000U) /* CK00 - fCLK */
#define _0001_TAU_CK00_fCLK_1                   (0x0001U) /* CK00 - fCLK/2^1 */
#define _0002_TAU_CK00_fCLK_2                   (0x0002U) /* CK00 - fCLK/2^2 */
#define _0003_TAU_CK00_fCLK_3                   (0x0003U) /* CK00 - fCLK/2^3 */
#define _0004_TAU_CK00_fCLK_4                   (0x0004U) /* CK00 - fCLK/2^4 */
#define _0005_TAU_CK00_fCLK_5                   (0x0005U) /* CK00 - fCLK/2^5 */
#define _0006_TAU_CK00_fCLK_6                   (0x0006U) /* CK00 - fCLK/2^6 */
#define _0007_TAU_CK00_fCLK_7                   (0x0007U) /* CK00 - fCLK/2^7 */
#define _0008_TAU_CK00_fCLK_8                   (0x0008U) /* CK00 - fCLK/2^8 */
#define _0009_TAU_CK00_fCLK_9                   (0x0009U) /* CK00 - fCLK/2^9 */
#define _000A_TAU_CK00_fCLK_10                  (0x000AU) /* CK00 - fCLK/2^10 */
#define _000B_TAU_CK00_fCLK_11                  (0x000BU) /* CK00 - fCLK/2^11 */
#define _000C_TAU_CK00_fCLK_12                  (0x000CU) /* CK00 - fCLK/2^12 */
#define _000D_TAU_CK00_fCLK_13                  (0x000DU) /* CK00 - fCLK/2^13 */
#define _000E_TAU_CK00_fCLK_14                  (0x000EU) /* CK00 - fCLK/2^14 */
#define _000F_TAU_CK00_fCLK_15                  (0x000FU) /* CK00 - fCLK/2^15 */
/* Selection of operation clock (PRS013 - PRS010) */
#define _0000_TAU_CK01_fCLK_0                   (0x0000U) /* CK01 - fCLK */
#define _0010_TAU_CK01_fCLK_1                   (0x0010U) /* CK01 - fCLK/2^1 */
#define _0020_TAU_CK01_fCLK_2                   (0x0020U) /* CK01 - fCLK/2^2 */
#define _0030_TAU_CK01_fCLK_3                   (0x0030U) /* CK01 - fCLK/2^3 */
#define _0040_TAU_CK01_fCLK_4                   (0x0040U) /* CK01 - fCLK/2^4 */
#define _0050_TAU_CK01_fCLK_5                   (0x0050U) /* CK01 - fCLK/2^5 */
#define _0060_TAU_CK01_fCLK_6                   (0x0060U) /* CK01 - fCLK/2^6 */
#define _0070_TAU_CK01_fCLK_7                   (0x0070U) /* CK01 - fCLK/2^7 */
#define _0080_TAU_CK01_fCLK_8                   (0x0080U) /* CK01 - fCLK/2^8 */
#define _0090_TAU_CK01_fCLK_9                   (0x0090U) /* CK01 - fCLK/2^9 */
#define _00A0_TAU_CK01_fCLK_10                  (0x00A0U) /* CK01 - fCLK/2^10 */
#define _00B0_TAU_CK01_fCLK_11                  (0x00B0U) /* CK01 - fCLK/2^11 */
#define _00C0_TAU_CK01_fCLK_12                  (0x00C0U) /* CK01 - fCLK/2^12 */
#define _00D0_TAU_CK01_fCLK_13                  (0x00D0U) /* CK01 - fCLK/2^13 */
#define _00E0_TAU_CK01_fCLK_14                  (0x00E0U) /* CK01 - fCLK/2^14 */
#define _00F0_TAU_CK01_fCLK_15                  (0x00F0U) /* CK01 - fCLK/2^15 */
/* Selection of operation clock (PRS021 - PRS020) */
#define _0000_TAU_CK02_fCLK_1                   (0x0000U) /* CK02 - fCLK/2^1 */
#define _0100_TAU_CK02_fCLK_2                   (0x0100U) /* CK02 - fCLK/2^2 */
#define _0200_TAU_CK02_fCLK_4                   (0x0200U) /* CK02 - fCLK/2^4 */
#define _0300_TAU_CK02_fCLK_6                   (0x0300U) /* CK02 - fCLK/2^6 */
/* Selection of operation clock (PRS031 - PRS030) */
#define _0000_TAU_CK03_fCLK_8                   (0x0000U) /* CK03 - fCLK/2^8 */
#define _1000_TAU_CK03_fCLK_10                  (0x1000U) /* CK03 - fCLK/2^10 */
#define _2000_TAU_CK03_fCLK_12                  (0x2000U) /* CK03 - fCLK/2^12 */
#define _3000_TAU_CK03_fCLK_14                  (0x3000U) /* CK03 - fCLK/2^14 */

/*
    Timer Mode Register 0n (TMR0n)
*/
/* Selection of operation clock (fMCK) of channel n (CKS0n1 - CKS0n0) */
#define _0000_TAU_CLOCK_SELECT_CK00             (0x0000U) /* operation clock CK00 set by timer clock select register 0 (TPS0) */
#define _8000_TAU_CLOCK_SELECT_CK01             (0x8000U) /* operation clock CK01 set by timer clock select register 0 (TPS0) */
#define _4000_TAU_CLOCK_SELECT_CK02             (0x4000U) /* operation clock CK02 set by timer clock select register 0 (TPS0) */
#define _C000_TAU_CLOCK_SELECT_CK03             (0xC000U) /* operation clock CK03 set by timer clock select register 0 (TPS0) */
/* Selection of count clock (fTCLK) of channel n (CCS0n) */
#define _0000_TAU_CLOCK_MODE_CKS                (0x0000U) /* operation clock (fMCK) specified by the CKS0n0 and CKS0n1 bits */
#define _1000_TAU_CLOCK_MODE_TI0N               (0x1000U) /* valid edge of input signal input from TI0n pin */
/* Selection of slave/master of channel n (MASTER0n) */
#define _0000_TAU_COMBINATION_SLAVE             (0x0000U) /* operates as slave channel */
#define _0800_TAU_COMBINATION_MASTER            (0x0800U) /* operates as master channel */
/* Selection of 8 or 16-bit timer operation for channels 1 and 3 (SPLIT0n) */
#define _0000_TAU_16BITS_MODE                   (0x0000U) /* operates as 16 bits timer */  
#define _0800_TAU_8BITS_MODE                    (0x0800U) /* operates as 8 bits timer */
/* Setting of start trigger or capture trigger of channel n (STS0n2 - STS0n0) */
#define _0000_TAU_TRIGGER_SOFTWARE              (0x0000U) /* only software trigger start is valid */
#define _0100_TAU_TRIGGER_TI0N_VALID            (0x0100U) /* TI0n input edge is used as a start/capture trigger */
#define _0200_TAU_TRIGGER_TI0N_BOTH             (0x0200U) /* TI0n input edges are used as a start/capture trigger */
#define _0400_TAU_TRIGGER_MASTER_INT            (0x0400U) /* interrupt signal of the master channel is used */
/* Selection of TI0n pin input valid edge (CIS0n1 - CIS0n0) */
#define _0000_TAU_TI0N_EDGE_FALLING             (0x0000U) /* falling edge */
#define _0040_TAU_TI0N_EDGE_RISING              (0x0040U) /* rising edge */
#define _0080_TAU_TI0N_EDGE_BOTH_LOW            (0x0080U) /* both edges (when low-level width is measured) */
#define _00C0_TAU_TI0N_EDGE_BOTH_HIGH           (0x00C0U) /* both edges (when high-level width is measured) */
/* Operation mode of channel n (MD0n3 - MD0n1) */
#define _0000_TAU_MODE_INTERVAL_TIMER           (0x0000U) /* interval timer mode */
#define _0004_TAU_MODE_CAPTURE                  (0x0004U) /* capture mode */
#define _0006_TAU_MODE_EVENT_COUNT              (0x0006U) /* event counter mode */
#define _0008_TAU_MODE_ONE_COUNT                (0x0008U) /* one count mode */
#define _000C_TAU_MODE_HIGHLOW_MEASURE          (0x000CU) /* high-/low-level width measurement mode */
#define _0001_TAU_MODE_PWM_MASTER               (0x0001U) /* PWM function (master channel) mode */
#define _0009_TAU_MODE_PWM_SLAVE                (0x0009U) /* PWM function (slave channel) mode */
#define _0008_TAU_MODE_ONESHOT                  (0x0008U) /* one-shot pulse output mode */
/* Setting of starting counting and interrupt (MD0n0) */
#define _0000_TAU_START_INT_UNUSED              (0x0000U) /* interrupt is not generated when counting is started */
#define _0001_TAU_START_INT_USED                (0x0001U) /* interrupt is generated when counting is started */

/*
    Timer Status Register 0n (TSR0n)
*/
/* Counter overflow status of channel n (OVF) */
#define _0000_TAU_OVERFLOW_NOT_OCCURS           (0x0000U) /* overflow does not occur */
#define _0001_TAU_OVERFLOW_OCCURS               (0x0001U) /* overflow occurs */

/*
    Timer Channel Enable Status Register 0 (TE0)
*/
/* Indication of operation enable/stop status of channel 0 (TE00) */
#define _0000_TAU_CH0_OPERATION_STOP            (0x0000U) /* operation is stopped */
#define _0001_TAU_CH0_OPERATION_ENABLE          (0x0001U) /* operation is enabled */
/* Indication of operation enable/stop status of channel 1 (TE01) */
#define _0000_TAU_CH1_OPERATION_STOP            (0x0000U) /* operation is stopped */
#define _0002_TAU_CH1_OPERATION_ENABLE          (0x0002U) /* operation is enabled */
/* Indication of operation enable/stop status of channel 2 (TE02) */
#define _0000_TAU_CH2_OPERATION_STOP            (0x0000U) /* operation is stopped */
#define _0004_TAU_CH2_OPERATION_ENABLE          (0x0004U) /* operation is enabled */
/* Indication of operation enable/stop status of channel 3 (TE03) */
#define _0000_TAU_CH3_OPERATION_STOP            (0x0000U) /* operation is stopped */
#define _0008_TAU_CH3_OPERATION_ENABLE          (0x0008U) /* operation is enabled */
/* Indication of operation enable/stop status of channel 4 (TE04) */
#define _0000_TAU_CH4_OPERATION_STOP            (0x0000U) /* operation is stopped */
#define _0010_TAU_CH4_OPERATION_ENABLE          (0x0010U) /* operation is enabled */
/* Indication of operation enable/stop status of channel 5 (TE05) */
#define _0000_TAU_CH5_OPERATION_STOP            (0x0000U) /* operation is stopped */
#define _0020_TAU_CH5_OPERATION_ENABLE          (0x0020U) /* operation is enabled */
/* Indication of operation enable/stop status of channel 6 (TE06) */
#define _0000_TAU_CH6_OPERATION_STOP            (0x0000U) /* operation is stopped */
#define _0040_TAU_CH6_OPERATION_ENABLE          (0x0040U) /* operation is enabled */
/* Indication of operation enable/stop status of channel 7 (TE07) */
#define _0000_TAU_CH7_OPERATION_STOP            (0x0000U) /* operation is stopped */
#define _0080_TAU_CH7_OPERATION_ENABLE          (0x0080U) /* operation is enabled */
/* Indication of operation enable/stop status of channel 1 higher 8 bits (TEH01) */
#define _0000_TAU_CH1_H8_OPERATION_STOP         (0x0000U) /* operation is stopped */
#define _0200_TAU_CH1_H8_OPERATION_ENABLE       (0x0200U) /* operation is enabled */
/* Indication of operation enable/stop status of channel 3 higher 8 bits (TEH03) */
#define _0000_TAU_CH3_H8_OPERATION_STOP         (0x0000U) /* operation is stopped */
#define _0800_TAU_CH3_H8_OPERATION_ENABLE       (0x0800U) /* operation is enabled */

/*
    Timer Channel Start Register 0 (TS0)
*/
/* Operation enable (start) trigger of channel 0 (TS00) */
#define _0000_TAU_CH0_START_TRG_OFF             (0x0000U) /* no trigger operation */
#define _0001_TAU_CH0_START_TRG_ON              (0x0001U) /* operation is enabled (start trigger is generated) */
/* Operation enable (start) trigger of channel 1 (TS01) */
#define _0000_TAU_CH1_START_TRG_OFF             (0x0000U) /* no trigger operation */
#define _0002_TAU_CH1_START_TRG_ON              (0x0002U) /* operation is enabled (start trigger is generated) */
/* Operation enable (start) trigger of channel 2 (TS02) */
#define _0000_TAU_CH2_START_TRG_OFF             (0x0000U) /* no trigger operation */
#define _0004_TAU_CH2_START_TRG_ON              (0x0004U) /* operation is enabled (start trigger is generated) */
/* Operation enable (start) trigger of channel 3 (TS03) */
#define _0000_TAU_CH3_START_TRG_OFF             (0x0000U) /* no trigger operation */
#define _0008_TAU_CH3_START_TRG_ON              (0x0008U) /* operation is enabled (start trigger is generated) */
/* Operation enable (start) trigger of channel 4 (TS04) */
#define _0000_TAU_CH4_START_TRG_OFF             (0x0000U) /* no trigger operation */
#define _0010_TAU_CH4_START_TRG_ON              (0x0010U) /* operation is enabled (start trigger is generated) */
/* Operation enable (start) trigger of channel 5 (TS05) */
#define _0000_TAU_CH5_START_TRG_OFF             (0x0000U) /* no trigger operation */
#define _0020_TAU_CH5_START_TRG_ON              (0x0020U) /* operation is enabled (start trigger is generated) */
/* Operation enable (start) trigger of channel 6 (TS06) */
#define _0000_TAU_CH6_START_TRG_OFF             (0x0000U) /* no trigger operation */
#define _0040_TAU_CH6_START_TRG_ON              (0x0040U) /* operation is enabled (start trigger is generated) */
/* Operation enable (start) trigger of channel 7 (TS07) */
#define _0000_TAU_CH7_START_TRG_OFF             (0x0000U) /* no trigger operation */
#define _0080_TAU_CH7_START_TRG_ON              (0x0080U) /* operation is enabled (start trigger is generated) */
/* Operation enable (start) trigger of channel 1 higher 8 bits (TSH01) */
#define _0000_TAU_CH1_H8_START_TRG_OFF          (0x0000U) /* no trigger operation */
#define _0200_TAU_CH1_H8_START_TRG_ON           (0x0200U) /* operation is enabled (start trigger is generated) */
/* Operation enable (start) trigger of channel 3 higher 8 bits (TSH03) */
#define _0000_TAU_CH3_H8_START_TRG_OFF          (0x0000U) /* no trigger operation */
#define _0800_TAU_CH3_H8_START_TRG_ON           (0x0800U) /* operation is enabled (start trigger is generated) */

/*
    Timer Channel Stop Register 0 (TT0)
*/
/* Operation stop trigger of channel 0 (TT00) */
#define _0000_TAU_CH0_STOP_TRG_OFF              (0x0000U) /* no trigger operation */
#define _0001_TAU_CH0_STOP_TRG_ON               (0x0001U) /* operation is stopped (stop trigger is generated) */
/* Operation stop trigger of channel 1 (TT01) */
#define _0000_TAU_CH1_STOP_TRG_OFF              (0x0000U) /* no trigger operation */
#define _0002_TAU_CH1_STOP_TRG_ON               (0x0002U) /* operation is stopped (stop trigger is generated) */
/* Operation stop trigger of channel 2 (TT02) */
#define _0000_TAU_CH2_STOP_TRG_OFF              (0x0000U) /* no trigger operation */
#define _0004_TAU_CH2_STOP_TRG_ON               (0x0004U) /* operation is stopped (stop trigger is generated) */
/* Operation stop trigger of channel 3 (TT03) */
#define _0000_TAU_CH3_STOP_TRG_OFF              (0x0000U) /* no trigger operation */
#define _0008_TAU_CH3_STOP_TRG_ON               (0x0008U) /* operation is stopped (stop trigger is generated) */
/* Operation stop trigger of channel 4 (TT04) */
#define _0000_TAU_CH4_STOP_TRG_OFF              (0x0000U) /* no trigger operation */
#define _0010_TAU_CH4_STOP_TRG_ON               (0x0010U) /* operation is stopped (stop trigger is generated) */
/* Operation stop trigger of channel 5 (TT05) */
#define _0000_TAU_CH5_STOP_TRG_OFF              (0x0000U) /* no trigger operation */
#define _0020_TAU_CH5_STOP_TRG_ON               (0x0020U) /* operation is stopped (stop trigger is generated) */
/* Operation stop trigger of channel 6 (TT06) */
#define _0000_TAU_CH6_STOP_TRG_OFF              (0x0000U) /* no trigger operation */
#define _0040_TAU_CH6_STOP_TRG_ON               (0x0040U) /* operation is stopped (stop trigger is generated) */
/* Operation stop trigger of channel 7 (TT07) */
#define _0000_TAU_CH7_STOP_TRG_OFF              (0x0000U) /* no trigger operation */
#define _0080_TAU_CH7_STOP_TRG_ON               (0x0080U) /* operation is stopped (stop trigger is generated) */
/* Operation stop trigger of channel 1 higher 8 bits (TTH01) */
#define _0000_TAU_CH1_H8_STOP_TRG_OFF           (0x0000U) /* no trigger operation */
#define _0200_TAU_CH1_H8_STOP_TRG_ON            (0x0200U) /* operation is stopped (stop trigger is generated) */
/* Operation stop trigger of channel 3 higher 8 bits (TTH03) */
#define _0000_TAU_CH3_H8_STOP_TRG_OFF           (0x0000U) /* no trigger operation */
#define _0800_TAU_CH3_H8_STOP_TRG_ON            (0x0800U) /* operation is stopped (stop trigger is generated) */

/*
    Timer Input Select Register m (TIS0)
*/
/* Selection of timer input used with channel 5 (TIS02 - TIS00) */
#define _00_TAU_CH5_INPUT_TI05                  (0x00U) /* input signal of timer input pin (TI05) */
#define _04_TAU_CH5_INPUT_fIL                   (0x04U) /* low-speed on-chip oscillator clock (fIL) */

/*
    Timer Output Enable Register 0 (TOE0)
*/
/* Timer output enable/disable of channel 0 (TOE00) */
#define _0001_TAU_CH0_OUTPUT_ENABLE             (0x0001U) /* enable output of timer */
#define _0000_TAU_CH0_OUTPUT_DISABLE            (0x0000U) /* disable output of timer */
/* Timer output enable/disable of channel 1 (TOE01) */
#define _0002_TAU_CH1_OUTPUT_ENABLE             (0x0002U) /* enable output of timer */
#define _0000_TAU_CH1_OUTPUT_DISABLE            (0x0000U) /* disable output of timer */
/* Timer output enable/disable of channel 2 (TOE02) */
#define _0004_TAU_CH2_OUTPUT_ENABLE             (0x0004U) /* enable output of timer */
#define _0000_TAU_CH2_OUTPUT_DISABLE            (0x0000U) /* disable output of timer */
/* Timer output enable/disable of channel 3 (TOE03) */
#define _0008_TAU_CH3_OUTPUT_ENABLE             (0x0008U) /* enable output of timer */
#define _0000_TAU_CH3_OUTPUT_DISABLE            (0x0000U) /* disable output of timer */
/* Timer output enable/disable of channel 4 (TOE04) */
#define _0010_TAU_CH4_OUTPUT_ENABLE             (0x0010U) /* enable output of timer */
#define _0000_TAU_CH4_OUTPUT_DISABLE            (0x0000U) /* disable output of timer */
/* Timer output enable/disable of channel 5 (TOE05) */
#define _0020_TAU_CH5_OUTPUT_ENABLE             (0x0020U) /* enable output of timer */
#define _0000_TAU_CH5_OUTPUT_DISABLE            (0x0000U) /* disable output of timer */
/* Timer output enable/disable of channel 6 (TOE06) */
#define _0040_TAU_CH6_OUTPUT_ENABLE             (0x0040U) /* enable output of timer */
#define _0000_TAU_CH6_OUTPUT_DISABLE            (0x0000U) /* disable output of timer */
/* Timer output enable/disable of channel 7 (TOE07) */
#define _0080_TAU_CH7_OUTPUT_ENABLE             (0x0080U) /* enable output of timer */
#define _0000_TAU_CH7_OUTPUT_DISABLE            (0x0000U) /* disable output of timer */

/*
    Timer Output Register 0 (TO0)
*/
/* Timer output of channel 0 (TO00) */
#define _0000_TAU_CH0_OUTPUT_VALUE_0            (0x0000U) /* timer output value is "0" */
#define _0001_TAU_CH0_OUTPUT_VALUE_1            (0x0001U) /* timer output value is "1" */
/* Timer output of channel 1 (TO01) */
#define _0000_TAU_CH1_OUTPUT_VALUE_0            (0x0000U) /* timer output value is "0" */
#define _0002_TAU_CH1_OUTPUT_VALUE_1            (0x0002U) /* timer output value is "1" */
/* Timer output of channel 2 (TO02) */
#define _0000_TAU_CH2_OUTPUT_VALUE_0            (0x0000U) /* timer output value is "0" */
#define _0004_TAU_CH2_OUTPUT_VALUE_1            (0x0004U) /* timer output value is "1" */
/* Timer output of channel 3 (TO03) */
#define _0000_TAU_CH3_OUTPUT_VALUE_0            (0x0000U) /* timer output value is "0" */
#define _0008_TAU_CH3_OUTPUT_VALUE_1            (0x0008U) /* timer output value is "1" */
/* Timer output of channel 4 (TO04) */
#define _0000_TAU_CH4_OUTPUT_VALUE_0            (0x0000U) /* timer output value is "0" */
#define _0010_TAU_CH4_OUTPUT_VALUE_1            (0x0010U) /* timer output value is "1" */
/* Timer output of channel 5 (TO05) */
#define _0000_TAU_CH5_OUTPUT_VALUE_0            (0x0000U) /* timer output value is "0" */
#define _0020_TAU_CH5_OUTPUT_VALUE_1            (0x0020U) /* timer output value is "1" */
/* Timer output of channel 6 (TO06) */
#define _0000_TAU_CH6_OUTPUT_VALUE_0            (0x0000U) /* timer output value is "0" */
#define _0040_TAU_CH6_OUTPUT_VALUE_1            (0x0040U) /* timer output value is "1" */
/* Timer output of channel 7 (TO07) */
#define _0000_TAU_CH7_OUTPUT_VALUE_0            (0x0000U) /* timer output value is "0" */
#define _0080_TAU_CH7_OUTPUT_VALUE_1            (0x0080U) /* timer output value is "1" */

/*
    Timer Output Level Register 0 (TOL0)
*/
/* Control of timer output level of channel 1 (TOL01) */
#define _0000_TAU_CH1_OUTPUT_LEVEL_H            (0x0000U) /* positive logic output (active-high) */
#define _0002_TAU_CH1_OUTPUT_LEVEL_L            (0x0002U) /* negative logic output (active-low) */
/* Control of timer output level of channel 2 (TOL02) */
#define _0000_TAU_CH2_OUTPUT_LEVEL_H            (0x0000U) /* positive logic output (active-high) */
#define _0004_TAU_CH2_OUTPUT_LEVEL_L            (0x0004U) /* negative logic output (active-low) */
/* Control of timer output level of channel 3 (TOL03) */
#define _0000_TAU_CH3_OUTPUT_LEVEL_H            (0x0000U) /* positive logic output (active-high) */
#define _0008_TAU_CH3_OUTPUT_LEVEL_L            (0x0008U) /* negative logic output (active-low) */
/* Control of timer output level of channel 4 (TOL04) */
#define _0000_TAU_CH4_OUTPUT_LEVEL_H            (0x0000U) /* positive logic output (active-high) */
#define _0010_TAU_CH4_OUTPUT_LEVEL_L            (0x0010U) /* negative logic output (active-low) */
/* Control of timer output level of channel 5 (TOL05) */
#define _0000_TAU_CH5_OUTPUT_LEVEL_H            (0x0000U) /* positive logic output (active-high) */
#define _0020_TAU_CH5_OUTPUT_LEVEL_L            (0x0020U) /* negative logic output (active-low) */
/* Control of timer output level of channel 6 (TOL06) */
#define _0000_TAU_CH6_OUTPUT_LEVEL_H            (0x0000U) /* positive logic output (active-high) */
#define _0040_TAU_CH6_OUTPUT_LEVEL_L            (0x0040U) /* negative logic output (active-low) */
/* Control of timer output level of channel 7 (TOL07) */
#define _0000_TAU_CH7_OUTPUT_LEVEL_H            (0x0000U) /* positive logic output (active-high) */
#define _0080_TAU_CH7_OUTPUT_LEVEL_L            (0x0080U) /* negative logic output (active-low) */

/*
    Timer Output Mode Register 0 (TOM0)
*/
/* Control of timer output mode of channel 1 (TOM01) */
#define _0000_TAU_CH1_OUTPUT_TOGGLE             (0x0000U) /* master channel output mode */
#define _0002_TAU_CH1_OUTPUT_COMBIN             (0x0002U) /* slave channel output mode */
/* Control of timer output mode of channel 2 (TOM02) */
#define _0000_TAU_CH2_OUTPUT_TOGGLE             (0x0000U) /* master channel output mode */
#define _0004_TAU_CH2_OUTPUT_COMBIN             (0x0004U) /* slave channel output mode */
/* Control of timer output mode of channel 3 (TOM03) */
#define _0000_TAU_CH3_OUTPUT_TOGGLE             (0x0000U) /* master channel output mode */
#define _0008_TAU_CH3_OUTPUT_COMBIN             (0x0008U) /* slave channel output mode */
/* Control of timer output mode of channel 4 (TOM04) */
#define _0000_TAU_CH4_OUTPUT_TOGGLE             (0x0000U) /* master channel output mode */
#define _0010_TAU_CH4_OUTPUT_COMBIN             (0x0010U) /* slave channel output mode */
/* Control of timer output mode of channel 5 (TOM05) */
#define _0000_TAU_CH5_OUTPUT_TOGGLE             (0x0000U) /* master channel output mode */
#define _0020_TAU_CH5_OUTPUT_COMBIN             (0x0020U) /* slave channel output mode */
/* Control of timer output mode of channel 6 (TOM06) */
#define _0000_TAU_CH6_OUTPUT_TOGGLE             (0x0000U) /* master channel output mode */
#define _0040_TAU_CH6_OUTPUT_COMBIN             (0x0040U) /* slave channel output mode */
/* Control of timer output mode of channel 7 (TOM07) */
#define _0000_TAU_CH7_OUTPUT_TOGGLE             (0x0000U) /* master channel output mode */
#define _0080_TAU_CH7_OUTPUT_COMBIN             (0x0080U) /* slave channel output mode */

/*
    Noise Filter Enable Register 1 (NFEN1)
*/
/* Enable/disable using noise filter of TI00 pin input signal (TNFEN00) */
#define _00_TAU_CH0_NOISE_OFF                   (0x00U) /* noise filter OFF */
#define _01_TAU_CH0_NOISE_ON                    (0x01U) /* noise filter ON */
/* Enable/disable using noise filter of TI01 pin input signal (TNFEN01) */
#define _00_TAU_CH1_NOISE_OFF                   (0x00U) /* noise filter OFF */
#define _02_TAU_CH1_NOISE_ON                    (0x02U) /* noise filter ON */
/* Enable/disable using noise filter of TI02 pin input signal (TNFEN02) */
#define _00_TAU_CH2_NOISE_OFF                   (0x00U) /* noise filter OFF */
#define _04_TAU_CH2_NOISE_ON                    (0x04U) /* noise filter ON */
/* Enable/disable using noise filter of TI03 pin input signal (TNFEN03) */
#define _00_TAU_CH3_NOISE_OFF                   (0x00U) /* noise filter OFF */
#define _08_TAU_CH3_NOISE_ON                    (0x08U) /* noise filter ON */
/* Enable/disable using noise filter of TI04 pin input signal (TNFEN04) */
#define _00_TAU_CH4_NOISE_OFF                   (0x00U) /* noise filter OFF */
#define _10_TAU_CH4_NOISE_ON                    (0x10U) /* noise filter ON */
/* Enable/disable using noise filter of TI05 pin input signal (TNFEN05) */
#define _00_TAU_CH5_NOISE_OFF                   (0x00U) /* noise filter OFF */
#define _20_TAU_CH5_NOISE_ON                    (0x20U) /* noise filter ON */
/* Enable/disable using noise filter of TI06 pin input signal (TNFEN06) */
#define _00_TAU_CH6_NOISE_OFF                   (0x00U) /* noise filter OFF */
#define _40_TAU_CH6_NOISE_ON                    (0x40U) /* noise filter ON */
/* Enable/disable using noise filter of TI07 pin input signal (TNFEN07) */
#define _00_TAU_CH7_NOISE_OFF                   (0x00U) /* noise filter OFF */
#define _80_TAU_CH7_NOISE_ON                    (0x80U) /* noise filter ON */

/***********************************************************************************************************************
Macro definitions
***********************************************************************************************************************/
/* 16-bit timer data register 00 (TDR00) */
#define _3E7F_TAU_TDR00_VALUE                   (0x3E7FU)
/* Clock divisor for TAU0 channel 0 */
#define TAU0_CHANNEL0_DIVISOR                   (1U)      /* fCLK */
/* 16-bit timer data register 01 (TDR01) */
#define _7CFF_TAU_TDR01_VALUE                   (0x7CFFU)
/* Clock divisor for TAU0 channel 1 */
#define TAU0_CHANNEL1_DIVISOR                   (1U)      /* fCLK */
/* 16-bit timer data register 02 (TDR02) */
#define _9C3F_TAU_TDR02_VALUE                   (0x9C3FU)
/* Clock divisor for TAU0 channel 2 */
#define TAU0_CHANNEL2_DIVISOR                   (2U)      /* fCLK/2 */

/***********************************************************************************************************************
Typedef definitions
***********************************************************************************************************************/

/***********************************************************************************************************************
Global functions
***********************************************************************************************************************/
void R_TAU0_Create(void);
void R_TAU0_Channel0_Start(void);
void R_TAU0_Channel0_Stop(void);
void R_TAU0_Channel1_Start(void);
void R_TAU0_Channel1_Stop(void);
void R_TAU0_Channel2_Start(void);
void R_TAU0_Channel2_Stop(void);

/* Start user code for function. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
#endif
